1. Field of the Invention
The present invention relates to an oscillator integrated circuit (IC), and more particularly to an RC oscillator IC including a capacitor.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating a conventional saw-tooth oscillator (also called a triangular oscillator). Conventional saw-tooth oscillators include first and second transistors M1 and M2, a capacitor CT, first and second comparators COMP1 and COMP2, and an RS flip-flop SR LATCH. The RS flip-flop includes an output terminal Q, such that the Q output terminal generates a saw-tooth wave signal as an output voltage Vo. If the output voltage Vo assumes a low level, the first transistor M1 is switched on, and the capacitor CT is charged with a first current I1. If the capacitor-voltage VCT is higher than a threshold voltage VT, the RS flip-flop (SR LATCH) is set so that the output voltage Vo assumes a high level. If the output voltage Vo is high, the first transistor M1 is switched off, and the second transistor M2 is switched on, such that the capacitor CT is discharged to a second current I2.
If the capacitor-voltage VCT is less than the reference voltage VB, the output signal of the second comparator COMP2 assumes a high level, such that the RS flip-flop SR LATCH is reset, and the output voltage Vo assumes a low level. If the output voltage Vo assumes a low level, the above-mentioned operation is repeated, resulting in an oscillation. Provided that the first current I1 and the second current I2 is approximately constant I, an oscillation period T can be represented by the following Equation 1, and an oscillation frequency f can be represented by the following equation 2:
                    T        =                  2          ⁢                                          ⁢                                    CT              ⁡                              (                                  VT                  -                  VB                                )                                      I                                              [                  Equation          ⁢                                          ⁢          1                ]                                f        =                  I                      2            ⁢                          sCT              ⁡                              (                                  VT                  -                  VB                                )                                                                        [                  Equation          ⁢                                          ⁢          2                ]            
Here “CT” is indicative of the capacitance of the capacitor CT. The above-mentioned saw-tooth oscillator may determine the first current I1 and the second current I2 using resistors, respectively. In this case, the oscillation frequency f is changed according to the resistance of the resistors. Oscillators containing a resistor and a capacitor are referred to as RC oscillators.
FIG. 2 is a circuit diagram illustrating a conventional RC oscillator. Conventional RC oscillators include first and second transistors M1 and M2, a capacitor CT, first and second comparators COMP1 and COMP2, a RS flip-flop SR LATCH, a first current mirror 110, a second current mirror 120, and a voltage/current converter 130. The first transistor M1 is connected to a second output terminal OUT2 of the first current mirror 110. A first output terminal OUT1 of the first current mirror 110 is connected to an input terminal IN of the second current mirror 120. The second transistor M2 is connected to an output terminal OUT of the second current mirror 120. The input terminal IN of the first current mirror 110 is connected to an external resistor RT via the voltage/current converter 130. In the above-mentioned configuration, a voltage signal applied to the resistor RT is indicative of a reference voltage VREF, and a current signal IRT applied to the resistor RT assumes the value of VREF/RT, the voltage VREF divided by the resistance of RT.
FIG. 3 is a circuit diagram illustrating an example of the current mirror of FIG. 2. If the first transistor M1 has the same characteristics as the second transistor M2, the ratio of the input current IN to the output current IO will be 1:1. However, typically the first transistor M1 has different characteristics than the second transistor M2. Due to this mismatch of the characteristics between the first and second transistors M1 and M2, the relationship, or ratio, between the input current and the output current will be 1:(1+A). Here A indicates the degree of mismatch, and is typically close to 0.
FIGS. 4-6 illustrate the layout and the operation of an active current mirror. A plurality of switches SW1-SW6 are arranged to solve the above-mentioned mismatch problem of FIG. 3. The switches SW1-SW6 perform a switching operation timed by a clock signal CLK or an inverse clock signal CLK.
The active current mirror is able to minimize the degree of the mismatch between the first transistor M1 and the second transistor M2 by the switching operation of the switches SW1-SW6. If the clock signal CLK assumes a high level, the switches are configured to implement the equivalent circuit of FIG. 5. The equivalent circuit of FIG. 5 operates in the same manner as in FIG. 3, and the output current IO can be represented by the following Equation 3:IO=(1+A)·IN  [Equation 3]
On the other hand, if the clock signal CLK assumes a low level, the inverse clock signal CLK assumes a high level, the switches SW2, SW5, and SW6 are switched on, to be configured as the equivalent circuit of FIG. 6. In this case, the output current IO can be represented by the following Equation 4:
                    IO        =                  IN                      1            +            A                                              [                  Equation          ⁢                                          ⁢          4                ]            
Provided that the clock signal CLK assumes the high and low levels for the same length of time, leading to a duty of essentially 50%, the output current IO will assume the value of Equation 3 and Equation 4 for the same length of time. Therefore, the average output current IO(AVG) can be represented by the following Equation 5:
                                                                        IO                ⁡                                  (                  AVG                  )                                            =                            ⁢                                                (                                      1                    +                    A                    +                                          1                                              1                        +                        A                                                                              )                                ·                                  IN                  2                                                                                                        ≈                            ⁢                                                (                                      1                    +                    A                    +                    1                    -                    A                    +                                          A                      2                                                        )                                ·                                  IN                  2                                                                                                        =                            ⁢                                                (                                      1                    +                                                                  A                        2                                            2                                                        )                                ⁢                IN                                                                        [                  Equation          ⁢                                          ⁢          5                ]            
As can be seen from Equation 5, the current output signal of the current mirror depends on the square of the mismatch A. For example, if the mismatch A equals 0.1, representing a 10% mismatch, the average output current IO(AVG) of the current mirror will change only by (0.1)2/2=0.005. This implementation lowers the influence of the mismatch on IO(AVG) considerably.
However, in order to operate the current mirror in the above manner, the duty of the clock signal needs to be maintained at 50% with high precision. This is not an easy task, as the conventional current mirrors do not receive external clock signals.
If a user desires to include a capacitor in an oscillator IC, the area covered by the capacitor must be minimized to improve an integration degree of the IC. For this reason, implementing the capacitor CT with high capacitance is not easy. A low capacitance for capacitor CT, however, leads to an undesirably high frequency.
Capacitor CT is charged or discharged with the current IRT. To address the above high frequency problem, the input current IRT is multiplied by 1/N using the current mirror of FIG. 3 or 4 for the discharging of the capacitor CT. This implementation will make the capacitor CT have the same effect as an N-times larger capacitor.
However, there are problems with the just-described approach. The characteristics-mismatch of elements of the current mirror is such a problem. Also, there may be a mismatch-dispersion, making it impossible to correctly generate a desired current signal lower than that of the apparent N-fold increased capacitor. The higher the current-division ratio N, the higher the degree and dispersion of the mismatch.